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參數(shù)資料
| 型號(hào)： | SII3512ECTU128 |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁(yè)數(shù)： | 88/132頁(yè) |
| 文件大小： | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
51
CONFIDENTIAL
PCI Bus Master – IDE0
Address Offset: 0x00
Access Type: Read/Write
Reset Value: 0x0000_XX00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
B
M
S
im
p
lex
P
B
M
DM
A
Cap
1
P
B
M
DM
A
Cap
0
Re
se
rve
d
IDE
0
DM
A
Com
p
P
B
M
E
rr
or
P
B
M
Ac
tive
IDE
Wat
ch
d
og
IDE
1
DM
A
Com
p
Software
Reserved
P
B
M
Rd
-Wr
Re
se
rve
d
P
B
M
E
n
ab
le
This register defines the PCI bus master register for IDE Channel #0 in the SiI3512 device. The register bits are defined
below.
Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
Bit [22]: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [20:19]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18]: IDE0 DMA Comp (R/W1C) – IDE0 DMA Completion Interrupt. During write DMA operation, this bit
set indicates that the IDE0 interrupt has been asserted and all data has been written to system memory. During
Read DMA, this bit set indicates that the IDE0 interrupt has been asserted. This bit must be W1C by software
when set during DMA operation (bit 0 is set). During normal operation, this bit reflects IDE0 interrupt line.
Bit [17]: PBM Error (R/W1C) – PCI Bus Master Error – IDE0. This bit set indicates that a PCI bus error
occurred while the SiI3512 controller was bus master. Additional information is available in the PCI Status
register in PCI Configuration space.
Bit [16]: PBM Active (R) – PCI Bus Master Active – IDE0. This bit set indicates that the SiI3512 controller is
currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers
have completed or PBM Enable bit is not set.
Bit[15]: IDE Watchdog Timer Status (R) – This bit is an ORed result of bit 12 in IDE0 Task File Timing +
Configuration + Status and bit 12 of IDE1 Task File Timing + Configuration + Status registers. When set indicates
that either IDE0 or IDE1 Watchdog timer has expired.
Bit[14]: IDE1 Interrupt Status (R) – This bit is a copy of Bit[18] IDE1 DMA Completion Interrupt in PCI Bus
Master – IDE1.
Bit [13:08]: Software Data (R/W) – System Software Data Storage. This bit field is used for read/write data
storage by the system. The properties of this bit field are detailed below.
Table 23. Software Data Byte, Base Address 5, Offset 0x00
Bit Location
Default
Description
[13:12]
0bXX
Not cleared by any reset
[11:10]
0b00
Cleared by PCI reset
[09:08]
0bXX
Cleared only by a D0–D3 power state change
Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from IDE0 to system memory. This bit is cleared to specify a DMA read operation from system memory
to an IDE0 device.
Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – IDE0. This bit is set to enable PCI bus master
operations for IDE Channel #0. PCI bus master operations can be halted by clearing this bit, but will erase all state
information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be
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|---|---|
| SII3531 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
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| SII3611 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:SATALink Device Bridge |
| SII3611CT80-1.5 | 制造商:SILICON IMAGE 功能描述:3611CT80-1.5 |
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