
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
102
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
Inputs
Register
7
6
5
4
3
2
1
0
Features
Current
0xF1
Previous (Expanded)
0x12
Sector Count
Current
na
Previous (Expanded)
na
LBA Low
Current
na
Previous (Expanded)
na
LBA Mid
Current
na
Previous (Expanded)
na
LBA High
Current
na
Previous (Expanded)
na
Device
obs
na
obs
DEV
1
na
Command
0xB0
1.
The DEV bit usage in the Serial ATA specification must be followed.
Outputs
Register
7
6
5
4
3
2
1
0
Error
na
Sector Count
Current
na
Previous (Expanded)
na
LBA Low
Current
na
Previous (Expanded)
na
LBA Mid
Current
na
Previous (Expanded)
na
LBA High
Current
na
Previous (Expanded)
na
Device
obs
na
obs
DEV
1
na
Status
BSY
DRDY
na
2
1.
The DEV bit usage in the Serial ATA specification must be followed.
2.
Error bit will be ignored. Completion is determined by BSY = 0 and DRDY = 1 only.
Description
This command unlocks the SiI3512 to support vendor-specific commands. Once this command is executed, the SiI3512
will remain unlocked until:
A VS Lock command that returns the VS state to the default locked state, or;
A hardware reset, or COMINIT or COMRESET.
Note that the VS Unlock Individual command, the VS Unlock Reserved command and Soft Reset have no effect on the
VS state.
If a VS Unlock Individual command is issued afterwards, the SiI3512 controller will be unlocked for both
individual vendor-specific/reserved commands and other vendor-specific commands.
If a VS Unlock Reserved command is issued afterwards, the SiI3512 controller will be unlocked for both vendor-
specific and reserved commands.
If both VS Unlock Individual and VS Unlock Reserved are issued afterwards, the SiI3512 controller will be
unlocked for individual vendor-specific/reserved commands, as well as other vendor-specific and reserved
commands.
The SiI3512 will use the non-data (ext) protocol with this command. The SiI3512 will send this command to the Serial
ATA device. The following situations may happen:
Case 1: The Serial ATA device (native or bridge) responds with a completed status. Both sides are set up to
support this scheme.