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參數(shù)資料
| 型號： | SII3512ECTU128 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁數(shù)： | 24/132頁 |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
4
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
All other PCI cycles are ignored by the SiI3512 controller.
As a PCI master, the SiI3512 controller generates the following PCI bus operations:
Memory Read Multiple
Memory Read
Memory Write
PCI Configuration Space
This section describes how the SiI3512 controller implements the required PCI configuration register space. The intent of
the PCI configuration space definition is to provide an appropriate set of configuration registers that satisfy the needs of
current and anticipated system configuration mechanisms, without specifying those mechanisms or otherwise placing
constraints on their use. These registers allow for:
Full device relocation (including interrupt binding)
Installation, configurations, and booting without user interventions
System address map construction by device-independent software
Figure 2. Address Lines During Configuration Cycle
The SiI3512 controller responds only to Type 0 configuration cycles. Type 1 cycles, which pass a configuration request
on to another PCI bus, are ignored.
The address phase during a SiI3512 configuration cycle indicates the function number and register number being
addressed which can be decoded by observing the status of the address lines AD[31:0] (see Figure 2 above).
The value of the signal lines AD[7:2] during the address phase of configuration cycles selects the register of the
configuration space to access. Valid values are between 0 and 15, inclusive. Accessing registers outside this range results
in an all-0s value being returned on reads, and no action being taken on writes.
The Class Code register contains the Class Code, Sub-Class Code, and Register-Level Programming Interface registers.
All writable bits in the configuration space are reset to 0 by the hardware reset, PCI RESET (RST#) asserted. After reset,
the SiI3512 is disabled and will only respond to PCI configuration write and PCI configuration read cycles.
Deviations from the Specification
The SiI3512 product has been developed and tested to the specification listed in this document. As a result of testing and
customer feedback, we may become aware of deviations to the specification that could affect the component's operation.
It is important that you have the most current version of this specification. If there are any questions, please contact
Silicon Image, Inc.
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相關代理商/技術參數(shù) |
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|---|---|
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
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| SII3531ACNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 48-Pin QFN EP |
| SII3611 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge |
| SII3611CT80-1.5 | 制造商:SILICON IMAGE 功能描述:3611CT80-1.5 |
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