參數(shù)資料
型號: SII3512ECTU128
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PQFP128
封裝: LEAD FREE, TQFP-128
文件頁數(shù): 33/132頁
文件大小: 3011K
代理商: SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
120
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
Appendix: SiI3512 NAND Tree
A NAND tree is available in the SiI3512 for functional testing of input pins. The NAND tree test mode can be invoked by
setting the following signals in the SiI3512:
Table 47. Signal Settings to Invoke NAND Tree Test Mode
Pin Name
Pin Number
Logic State
TEST_MODE
57
1
FL_ADDR[18]
56
0
FL_ADDR[17]
55
0
FL_ADDR[16]
54
1
FL_ADDR[15]
53
0
The NAND tree is shown in the following diagram:
Figure 15. Input Pin Testing NAND Tree
The test decoder generates the NAND tree signal. This signal performs the following functions:
1)
Drives the enable pins of all the bi-directional I/Os and sets them in input mode. The only exception is the
FL_DATA00 pin, which is used as the output for the NAND tree.
2)
Drives the output multiplexer to direct the output of the NAND tree to the FL_DATA00 pin.
Test
Decoder
Test_mode
Fl_addr[18:15]
Input 1
Input 2
Input 3
Input n
Vdd
Nand_tree
Fl_data00
Test
Decoder
Test_mode
Fl_addr[18:15]
Input 1
Input 2
Input 3
Input n
Vdd
Nand_tree
Fl_data00
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