
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
16
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
Pin Number: 31
When PCI_RST_N is de-asserted, this pin is an output and represents flash memory address bit 0. During reset,
it is sampled to configure Mass Storage class or RAID mode in the PCI Class Code register. A high on this pin
sets Mass Storage class, a low sets RAID mode. The configuration state is latched internally when PCI_RST_N
is de-asserted. This pad is internally pulled high to enable Mass Storage class if left unconnected.
Pin Name: FL_ADDR[01] / BA5_EN
Pin Number: 32
When PCI_RST_N is de-asserted, this pin is an output and represents flash memory address bit 1. During reset,
it is sampled to configure Base Address Register 5. A high on this pin enables Base Address Register 5, a low
disables Base Address Register 5. The configuration state is latched internally when PCI_RST_N is de-asserted.
This pin is internally pulled high to enable Base address register 5 when left unconnected.
Pin Name: FL_ADDR[02-18]
Pin Numbers: 33, 36~39, 42~46, 49~50, 52~56
Flash Memory address bits; 19 total for 512k address space. Flash address pins 15 to 18 are used to select
internal test modes in conjunction with the TEST_MODE pin; they have internal pull-downs and must be
unconnected or pulled down.
Pin Name: FL_DATA[00-07]
Pin Numbers: 58~65
8-bit flash memory data bus.
Pin Name: FL_RD_N
Pin Number: 35
Flash read enable signal, active low.
Pin Name: FL_WR_N
Pin Number: 34
Flash write enable signal, active low.
Memory Chip Select
Pin Name: MEM_CS_N
Pin Number: 30
This pin is used to select and enable the external memory. It is active low.
Serial Interface Signals
Pin Name: EEPROM_SDAT
Pin Number: 2
Serial Interface data line.
Pin Name: EEPROM_SCLK
Pin Number: 3
Serial Interface clock.