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參數(shù)資料
| 型號(hào)： | SII3512ECTU128 |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁(yè)數(shù)： | 32/132頁(yè) |
| 文件大小： | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
119
CONFIDENTIAL
EEPROM Memory Access
The SiI3512 supports an external 256-byte EEPROM memory device. Access to the EEPROM memory is available
through internal register operations in the SiI3512.
EEPROM Write Operation
Verify that bit 25 is cleared in the EEPROM Memory Address – Command + Status register at Offset 0x58 of
Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the
memory access is complete and ready for another operation.
Write 1‘ to clear bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error
occurred during a previous memory access.
Program the write address for the EEPROM memory access. The address field is defined by bits [07:00] in the
EEPROM Memory Address – Command + Status register. Program bits [15:08] to zero.
Program the write data for the EEPROM memory access. The data field is defined by bits [07:00] in the
EEPROM Memory Data register at Offset 0x5C of Base Address 5.
Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory
Address – Command + Status register. The bit must be cleared for a memory write access.
Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address – Command + Status
register.
Poll bit 25 in the EEPROM Memory Address – Command + Status register. The bit reads one when a memory
access is currently in progress. It reads zero when the memory access is complete.
Check bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error occurred
during a previous memory access.
EEPROM Read Operation
Verify that bit 25 is cleared in the EEPROM Memory Address – Command + Status register at offset 0x58 of
Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the
memory access is complete and ready for another operation.
Write 1‘ to clear bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error
occurred during a previous memory access.
Program the read address for the EEPROM memory access. The address field is defined by bits [07:00] in the
EEPROM Memory Address – Command + Status register. Program bits [15:08] to zero.
Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory
Address – Command + Status register. The bit must be set for a memory read access.
Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address – Command + Status
register.
Poll bit 25 in the EEPROM Memory Address – Command + Status register. The bit reads one when a memory
access is currently in progress. It reads zero when the memory access is complete.
Check bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error occurred
during a previous memory access.
Read the data from the EEPROM memory access. The data field is defined by bits [07:00] in the EEPROM
Memory Data register at Offset 0x5C of Base Address 5.
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| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
| SIO10N268-NU | MULTIFUNCTION PERIPHERAL, PQFP128 |
| SIS300 | GRAPHICS PROCESSOR, PBGA365 |
| SK12430PJT | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3531 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
| SII3531A | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI Express to Serial ATA Controller |
| SII3531ACNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 48-Pin QFN EP |
| SII3611 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:SATALink Device Bridge |
| SII3611CT80-1.5 | 制造商:SILICON IMAGE 功能描述:3611CT80-1.5 |
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