參數(shù)資料
型號： SII3512ECTU128
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP128
封裝： LEAD FREE, TQFP-128
文件頁數(shù)： 73/132頁
文件大?。?/td> 3011K
代理商： SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
37
CONFIDENTIAL
Power Management Control + Status
Address Offset: 0x64
Access Type: Read/Write
Reset Value: 0x6400_4000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PPM Data
Reserved
P
M
E
S
tat
u
s
P
M
Dat
a
S
cale
PPM Data Sel
P
M
E
n
a
Reserved
P
M
P
owe
r
S
tat
e
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:24]: PPM Data (R) – PCI Power Management Data. This bit field is hardwired to 0x64.
Bit [23:16]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15]: PME Status (R) – PME Status. This bit is hardwired to 0. The SiI3512 device does not support PME.
Bit [14:13]: PPM Data Scale (R) – PCI Power Management Data Scale. This bit field is hardwired to 0b10 to
indicate a scaling factor of 10 mW.
Bit [12:09]: PPM Data Sel (R/W) – PCI Power Management Data Select. This bit field is set by the system to
indicate which data field is to be reported through the PPM Data bits (although current implementation hardwires
the PPM Data to indicate 1 Watt).
Bit [08]: PME Ena (R) – PME Enable. This bit is hardwired to 0. The SiI3512 controller does not support PME.
Bit [07:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]: PPM Power State (R/W) – PCI Power Management Power State. This bit field is set by the system to
dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3 (Hot).
PCI Bus Master – IDE0
Address Offset: 0x70
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
B
M
S
im
p
lex
P
B
M
DM
A
Cap
1
P
B
M
DM
A
Cap
0
Re
se
rve
d
IDE
0
DM
A
Com
p
P
B
M
E
rr
or
P
B
M
Ac
tive
Reserved
P
B
M
Rd
-Wr
Re
se
rve
d
P
B
M
E
n
ab
le
This register defines the PCI bus master register for IDE Channel #0 in the SiI3512 controller. The register bits are also
mapped to Base Address 4, Offset 0x00, Base Address 5, Offset 0x00, and Base Address 5, Offset 0x10. See PCI Bus
Master – IDE0 section on page 51 for bit definitions.
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