參數(shù)資料
型號： SII3512ECTU128
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP128
封裝： LEAD FREE, TQFP-128
文件頁數(shù)： 75/132頁
文件大?。?/td> 3011K
代理商： SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
39
CONFIDENTIAL
Data Transfer Mode – IDE0
Address Offset: 0x80
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Re
se
rve
d
IDE
0
De
vice
1
T
ran
sf
er
M
od
e
Re
se
rve
d
IDE
0
De
vice
0
T
ran
sf
er
M
od
e
This register defines the transfer mode register for IDE Channel #0 in the SiI3512 controller. The register bits are also
mapped to Base Address 5, Offset 0xB4. See Data Transfer Mode – IDE0 section on page 67 for bit definitions.
Data Transfer Mode – IDE1
Address Offset: 0x84
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Re
se
rve
d
IDE
1
De
vice
1
T
ran
sf
er
M
od
e
Re
se
rve
d
IDE
1
De
vice
0
T
ran
sf
er
M
od
e
This register defines the transfer mode register for IDE Channel #1 in the SiI3512 controller. The register bits are also
mapped to Base Address 5, Offset 0xF4. See Data Transfer Mode – IDE1 section on page 72 for bit definitions.
System Configuration Status – Command
Address Offset: 0x88
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
IDE
1
In
t
B
lock
IDE
0
In
t
B
lock
Reserved
B
A5_E
N
Reserved
IDE
0
M
od
u
le
Rs
t
IDE
1
M
od
u
le
Rs
t
F
0
M
od
u
le
Rs
t
F
1
M
od
u
le
Rs
t
Re
se
rve
d
AR
B
M
od
u
le
Rs
t
P
B
M
od
u
le
Rs
t
This register defines the system configuration status and command register for the SiI3512 controller. The register bits
are also mapped to Base Address 5, Offset 0x48. See System Configuration Status – Command section on page 58 for bit
definitions.
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