參數(shù)資料
型號(hào)： SII3512ECTU128
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP128
封裝： LEAD FREE, TQFP-128
文件頁數(shù)： 79/132頁
文件大小： 3011K
代理商： SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
42
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
IDE1 Task File Configuration + Status
Address Offset: 0xB0
Access Type: Read/Write
Reset Value: 0x6515_0101
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
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Reserved
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This register defines the task file configuration and status register for IDE Channel #1 in the SiI3512 device. The register
bits are also mapped to Base Address 5, Offset 0xE0. See IDE1 Task File Configuration + Status section on page 71 for
bit definitions.
BA5 Indirect Address
Address Offset: 0xC0
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Address
This register permits the indirect addressing of registers normally referenced using Base Address 5. Any register that is
not accessible by any means other than via Base Address 5 is indirectly addressable. The following BA5 address ranges
are not indirectly accessible, but are accessible either in Configuration Space or via other Base Address registers: 0x00–
0x1C, 0x80–0x8C, 0xC0–0xCC.
BA5 Indirect Access
Address Offset: 0xC4
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
As defined for indirectly accessed register
This register provides the indirect access addressed by the BA5 Indirect Address register. The use of indirect access must
be enabled by setting bit 1 of the Configuration register (0x40).
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