參數(shù)資料
型號： SII3512ECTU128
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP128
封裝： LEAD FREE, TQFP-128
文件頁數(shù)： 31/132頁
文件大?。?/td> 3011K
代理商： SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
118
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
Flash and EEPROM Programming Sequences
Flash Memory Access
The SiI3512 supports an external flash memory device of up to 4-Mbit capacity. Access to the flash memory is available
through two means: PCI Direct Access and Register Access.
PCI Direct Access
Access to the Expansion ROM is enabled by setting bit 0 in the Expansion ROM Base Address register at offset 0x30 of
the PCI Configuration Space. When this bit is set, bits [31:19] of the same register are programmable by the
system to set the base address for all flash memory accesses. Read and write operations with the flash
memory are initiated by Memory Read and Memory Write commands on the PCI bus. Accesses may be as bytes, words,
or dwords.
Register Access
This type of flash memory access is carried out through a sequence of internal register read and write operations. The
proper programming sequences are detailed below.
Flash Write Operation
Verify that bit 25 is cleared in the register at Offset 0x50 of Base Address 5. The bit reads one when a memory
access is currently in progress.
It reads zero when the memory access is complete and ready for another operation.
Program the write address for the flash memory access. The address field is defined by bits [18:00] in the Flash
Memory Address – Command + Status register.
Program the write data for the flash memory access. The data field is defined by bits [07:00] in the Flash
Memory Data register at Offset 54 of Base Address 5.
Program the memory access type. The memory access type is defined by bit 24 in the Flash Memory Address –
Command + Status register. The bit must be cleared for a memory write access.
Initiate the flash memory access by setting bit 25 in the Flash Memory Address – Command + Status register.
Flash Read Operation
Verify that bit 25 is cleared in the Flash Memory Address – Command + Status register at Offset 0x50 of Base
Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the memory
access is complete and ready for another operation.
Program the read address for the flash memory access. The address field is defined by bits [18:00] in the Flash
Memory Address – Command + Status register.
Program the memory access type. The memory access type is defined by bit 24 in the Flash Memory Address –
Command + Status register. The bit must be set for a memory read access.
Initiate the flash memory access by setting bit 25 in the Flash Memory Address – Command + Status register.
Verify that bit 25 is cleared in the Flash Memory Address – Command + Status register. The bit reads one when
a memory access is currently in progress. It reads zero when the memory access is complete.
Read the data from the flash memory access. The data field is defined by bits [07:00] in the Flash Memory Data
register at Offset 0x54 of Base Address 5.
相關(guān)PDF資料
PDF描述
SII3531ACNU PCI BUS CONTROLLER, QCC48
SIO10N268-NU MULTIFUNCTION PERIPHERAL, PQFP128
SIS300 GRAPHICS PROCESSOR, PBGA365
SK12430PJT 800 MHz, OTHER CLOCK GENERATOR, PQCC28
SK12439PJ 800 MHz, OTHER CLOCK GENERATOR, PQCC28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII3531 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller
SII3531A 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to Serial ATA Controller
SII3531ACNU 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 48-Pin QFN EP
SII3611 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge
SII3611CT80-1.5 制造商:SILICON IMAGE 功能描述:3611CT80-1.5
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*