
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
15
CONFIDENTIAL
PCI Clock Signal
Pin Names: PCI_CLK
Pin Number: 69
Clock Signal provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals
(except PCI_RST_N, and PCI_INTA_N) are sampled on the rising edge of PCI_CLK. All other timing parameters are
defined with respect to this edge.
PCI Reset
Pin Name: PCI_RST_N
Pin Number: 68
PCI_RST_N is an active low input that is used to set the internal registers to their initial state. PCI_RST_N is typically
the system power-on reset signal as distributed on the PCI bus.
PCI M66EN
Pin Name: PCI_M66EN
Pin Number: 116
This pin configures the PCI bus operating frequency. When low, the PCI bus operates from 0 to 33 MHz. When high, the
PCI bus operates from 33 MHz to 66 MHz.
Miscellaneous I/O Pins
Ground
Pin Name: VSS
Pin Number: 41, 48, 76, 81, 92, 107, 113, and 123
Logic Ground. This ground pins are connected with GNDA (SerDes Ground) with an EPAD.
TEST
Pin Name: TEST_MODE
Pin Number: 57
This pin is used, in conjunction with other pins, to enable various test functions within the device.
Power Supply
Pin Name(s): VDDO
Pin Number(s): 28, 40, 75, 91, 106, and 122
Power Supply Input.
Pin Name(s): VDDI
Pin Number(s): 47, 80, and 112
Power Supply Input for internal core.
Internal Scan Test
Pin Name: SCAN_EN
Pin Number: 29
This pin, when active (high), will place all scan flip-flops into scan mode for chip testing. This pin must be left open or
tied to ground for normal operation.
LED Drivers
Pin Names: LED[0..1]
Pin Numbers: 51, 66
These are 12-mA open-drain outputs to drive Activity LEDs for IDE channels 0 and 1, respectively.
Flash Signals
Pin Name: FL_ADDR[00] / IDE_CFG