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參數(shù)資料
| 型號： | SII3512ECTU128 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁數(shù)： | 72/132頁 |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
36
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
Software Data Register
Address Offset: 0x44
Access Type: Read/Write
Reset Value: Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Software Data
This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are
never cleared by any type of reset.
Power Management Capabilities
Address Offset: 0x60
Access Type: Read Only
Reset Value: 0x0622_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PME Support
P
M
D2
S
u
p
or
t
P
M
D1
S
u
p
or
t
Auxiliary
Current
De
v
S
p
ec
ial
In
it
Re
se
rve
d
P
M
E
Cloc
k
PPM Rev
Next Item Pointer
Capability ID
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:27]: PME Support (R) – Power Management Event Support. This bit field is hardwired to 0x00 to indicate
that the SiI3512 device does not support PME.
Bit [26]: PPM D2 Support (R) – PCI Power Management D2 Support. This bit is hardwired to 1 to indicate
support for the D2 Power Management State.
Bit [25]: PPM D1 Support (R) – PCI Power Management D1 Support. This bit is hardwired to 1 to indicate
support for the D1 Power Management State.
Bit [24:22]: Auxiliary Current (R) – Auxiliary Current. This bit field is hardwired to 0b000.
Bit [21]: Dev Special Init (R) – Device Special Initialization. This bit is hardwired to 1 to indicate that the
SiI3512 controller requires special initialization
Bit [20]: Reserved (R). This bit is reserved and returns zero on a read.
Bit [19]: PME Clock (R) – Power Management Event Clock. This bit is hardwired to 0. The SiI3512 controller
does not support PME.
Bit [18:16]: PPM Rev (R) – PCI Power Management Revision. This bit field is hardwired to 0b010 to indicate
compliance with the PCI Power Management Interface Specification revision 1.1.
Bit [15:08]: Next Item Pointer (R) – PCI Additional Capability Next Item Pointer. This bit field is hardwired to
0x00 to indicate that there are no additional items on the Capabilities List.
Bit [07:00]: Capability ID (R) – PCI Additional Capability ID. This bit field is hardwired to 0x01 to indicate that
this Capabilities List is a PCI Power Management definition.
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PDF描述 |
|---|---|
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| SIS300 | GRAPHICS PROCESSOR, PBGA365 |
| SK12430PJT | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| SK12439PJ | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
| SII3531A | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to Serial ATA Controller |
| SII3531ACNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 48-Pin QFN EP |
| SII3611 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge |
| SII3611CT80-1.5 | 制造商:SILICON IMAGE 功能描述:3611CT80-1.5 |
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