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參數(shù)資料
| 型號(hào)： | SII3512ECTU128 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁(yè)數(shù)： | 82/132頁(yè) |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
45
CONFIDENTIAL
IDE1 Task File Register 0
Address Offset: 0x00
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Starting Sector
Number
IDE1 Task File Sector Count
IDE1 Task File Features (W)
IDE1 Task File Error (R)
IDE1 Data (byte access)
IDE1 Data (word access)
IDE1 Data (dword access)
This register defines four of the IDE Channel #1 Task File registers in the SiI3512 controller. The register bits are also
mapped to Base Address 5, Offset 0xC0. See IDE1 Task File Register 0 section on page 68 for bit definitions.
IDE1 Task File Register 1
Address Offset: 0x04
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Command + Status
IDE1 Task File Device+Head
IDE1 Task File Cylinder High
IDE1 Task File Cylinder Low
This register defines four of the IDE Channel #1 Task File registers in the SiI3512 controller. The register bits are also
mapped to Base Address 5, Offset 0xC4. See IDE1 Task File Register 1 section on page 68 for bit definitions.
Internal Register Space – Base Address 3
These registers are 32 bits wide and define the internal operation of the SiI3512 controller. The access types are defined
as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O
space.
Table 20. SiI3512 Internal Register Space – Base Address 3
Address
Offset
Register Name
Access
Type
31
16
15
00
0x00
Reserved
IDE1 TF Device
Control Auxiliary
Status
Reserved
R/W
IDE1 Task File Register 2
Address Offset: 0x00
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
IDE1 Task File Device Control
IDE1 Task File Auxiliary Status
Reserved
This register defines one of the IDE Channel #1 Task File registers in the SiI3512 device. The register bits are also
mapped to Base Address 5, Offset 0xC8. See IDE1 Task File Register 2 section on page 69 for bit definitions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
| SII3531A | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to Serial ATA Controller |
| SII3531ACNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 48-Pin QFN EP |
| SII3611 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge |
| SII3611CT80-1.5 | 制造商:SILICON IMAGE 功能描述:3611CT80-1.5 |
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