參數(shù)資料
型號(hào)： SII3512ECTU128
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP128
封裝： LEAD FREE, TQFP-128
文件頁數(shù)： 74/132頁
文件大小： 3011K
代理商： SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
38
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
PRD Table Address – IDE0
Address Offset: 0x74
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE0
Re
se
rve
d
This register defines the PRD Table Address register for IDE Channel #0 in the SiI3512 controller. The register bits are
also mapped to Base Address 4, Offset 0x04 and Base Address 5, Offset 0x04. See PRD Table Address – IDE0 section
on page 52 for bit definitions.
PCI Bus Master – IDE1
Address Offset: 0x78
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
B
M
S
im
p
lex
P
B
M
DM
A
Cap
1
P
B
M
DM
A
Cap
0
Re
se
rve
d
IDE
1
DM
A
Com
p
P
B
M
E
rr
or
P
B
M
Ac
tive
Reserved
P
B
M
Rd
-Wr
Re
se
rve
d
P
B
M
E
n
ab
le
This register defines the PCI bus master register for IDE Channel #1 in the SiI3512 device. The register bits are also
mapped to Base Address 4, Offset 0x08, Base Address 5, Offset 0x08, and Base Address 5, Offset 0x18. See PCI Bus
Master – IDE1 section on page 52 for bit definitions.
PRD Table Address – IDE1
Address Offset: 0x7C
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE1
Re
se
rve
d
This register defines the PRD Table Address register for IDE Channel #1 in the SiI3512 controller. The register bits are
also mapped to Base Address 4, Offset 0x0C and Base Address 5, Offset 0x0C. See PRD Table Address – IDE1 section
on page 53 for bit definitions.
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