參數(shù)資料
型號： SII3512ECTU128
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP128
封裝： LEAD FREE, TQFP-128
文件頁數(shù)： 66/132頁
文件大?。?/td> 3011K
代理商： SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
31
CONFIDENTIAL
Bit 01: Memory Space (R/W) – Memory Space Enable. This bit set enables the SiI3512 device to respond to PCI
memory space access.
Bit 00: IO Space (R/W) – IO Space Enable. This bit set enables the SiI3512 controller to respond to PCI IO space
access.
PCI Class Code – Revision ID
Address Offset: 0x08
Access Type: Read/Write
Reset Value: 0x0180_0001 or 0x0104_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PCI Class Code
PCI Prog Int
IDE
1
M
od
e
P
rog
IDE
1
P
wr
-Up
M
od
e
IDE
0
M
od
e
P
rog
IDE
0
P
wr
-U
p
M
od
e
Revision ID
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:08]: PCI Class Code (R) – PCI Class Code. This value in this bit field is determined by any one of three
options:
1)
The default value, set by an external jumper on the FL_ADDR[00]/IDE_CFG pin:
1.
If IDE_CFG = 0, the value is 0x010400 for RAID mode
2.
If IDE_CFG = 1, the value is 0x018000 for Mass Storage class
2)
Loaded from an external memory device: If an external memory device — flash or EEPROM — is
present with the correct signature, the PCI Class Code is loaded from that device after reset. See Auto-
Initialization section on page 25 for additional information.
3)
System programmable: If Bit 0 of the Configuration register (0x40) is set the three bytes are system
programmable.
Bit [07:00]: Revision ID (R) – Chip Revision ID. This bit field is hardwired to indicate the revision level of the
chip design; revision 0x01 is defined for the production version.
BIST – Header Type – Latency Timer – Cache Line Size
Address Offset: 0x0C
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BIST
Header Type
Latency Timer
Cache Line Size
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:24]: BIST (R) – This bit field is hardwired to 0x00.
Bit [23:16]: Header Type (R) – This bit field is hardwired to 0x00.
Bit [15:08]: Latency Timer (R/W). This bit field is used to specify the time in number of PCI clocks, the SiI3512
device as a master is still allowed to control the PCI bus after its GRANT_L is de-asserted. The lower four bits
[0B:08] are hardwired to 0x0, resulting in a time granularity of 16 clocks.
Bit [07:00]: Cache Line Size (R/W). This bit field is used to specify the system cache line size in terms of 32-bit
words. The upper 2 bits are not used, resulting in a maximum size of 64 32-bit words. With the SiI3512 controller
as a master, initiating a read transaction, it issues PCI command Read Multiple in place when empty space in its
FIFO is larger than the value programmed in this register. If this value is set to 0x00, SiI3512 controller will
disable PCI command Read Multiple.
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