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參數(shù)資料
| 型號(hào)： | SII3512ECTU128 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁(yè)數(shù)： | 47/132頁(yè) |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
13
CONFIDENTIAL
Pin Descriptions
66-MHz 32-bit PCI Pins
PCI Address and Data
Pin Names: PCI_AD[31..0]
Pin Numbers: 72~74, 77~79, 82~83, 86~90, 93~95, 108~111, 114~115, 117~118, 120~121, 124~128, 1
Address and Data buses are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by
one or more data phases. PCI supports both read and write bursts. The address phase is the first clock cycle in which
PCI_FRAME_N signal is asserted. During the address phase, PCI_AD[31:0] contain a physical address (32 bits). For
I/O, this can be a byte address. For configuration and memory it is a dword address. During data phases, PCI_AD[7:0]
contain the least significant byte (LSB) and PCI_AD[31:24] contain the most significant byte (MSB). Write data is stable
and valid when PCI_IRDY_N is asserted; read data is stable and valid when PCI_TRDY_N is asserted. Data is
transferred during those clocks where both PCI_IRDY_N and PCI_TRDY_N are asserted.
PCI Command and Byte Enables
Pin Names: PCI_CBE[3..0]
Pin Numbers: 84, 96, 105, 119
Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction,
PCI_CBE[3:0]_N define the bus command. During the data phase, PCI_CBE[3:0]_N are used as Byte Enables. Byte
Enables are valid for the entire data phase and determine which byte lanes carry meaningful data.
PCI ID Select
Pin Name: PCI_IDSEL
Pin Number: 85
This signal is used as a chip select during configuration read and write transactions.
PCI Frame Cycle
Pin Name: PCI_FRAME_N
Pin Number: 97
Cycle Frame is driven by the current master to indicate the beginning and duration of an access. PCI_FRAME_N is
asserted to indicate that a bus transaction is beginning. While PCI_FRAME_N is asserted, data transfers continue. When
PCI_FRAME_N is de-asserted, the transaction is in the final data phase or has completed.
PCI Initiator Ready
Pin Name: PCI_IRDY_N
Pin Number: 98
Initiator Ready indicates the initializing agent‘s (bus master‘s) ability to complete the current data phase of the
transaction. This signal is used with PCI_TRDY_N. A data phase is completed on any clock when both PCI_IRDY_N
and PCI_TRDY_N are sampled as asserted. Wait cycles are inserted until both PCI_IRDY_N and PCI_TRDY_N are
asserted together.
PCI Target Ready
Pin Name: PCI_TRDY_N
Pin Number: 102
Target Ready indicates the target agent‘s ability to complete the current data phase of the transaction. PCI_TRDY_N is
used with PCI_IRDY_N. A data phase is completed on any clock when both PCI_TRDY_N and PCI_IRDY_N are
sampled asserted. During a read, PCI_TRDY_N indicates that valid data is present on PCI_AD[31:0]. During a write, it
indicates the target is prepared to accept data.
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相關(guān)代理商/技術(shù)參數(shù) |
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