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參數(shù)資料
| 型號(hào)： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁(yè)數(shù)： | 95/121頁(yè) |
| 文件大小： | 1127K |
| 代理商： | S1C63653F |
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S1C63653 TECHNICAL MANUAL
EPSON
67
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.6 16-bit timer (timer 0 + timer 1)
Timers 0 and 1 can be used as a 16-bit timer.
To use the 16-bit timer, write "1" to the timer 0 16-bit mode selection register MOD16.
The 16-bit timer is configured with timer 0 for low-order byte and timer 1 for high-order byte as shown in
Figure 4.10.6.1.
Reload data register
RLD00–RLD07
Data buffer
PTD00–PTD07
Comparator
PTRUN0
FCSEL
PLPOL
Timer 0 + Timer 1
Timer 0
Timer 1
PTPS00
PTPS01
8-bit
down counter
8-bit
down counter
Prescaler
Selector
CKSEL0
Timer 0 Run/Stop
Clock
control
circuit
Timer function setting
Pulse polarity setting
Prescaler
setting
Under-
flow
signal
Compare match signal
Data
bus
8 low-order bits
8 high-order bits
Data buffer
PTD10–PTD17
Compare data register
CD00–CD07
Compare data register
CD10–CD17
Divider
OSC3
oscillation
circuit
OSC1
oscillation
circuit
fOSC3
fOSC1
Reload data register
RLD10–RLD17
Input port
K13
EVCNT
Event counter mode setting
K13
PTSEL1
PWM output selection
TOUT
Interrupt
PWM waveform
generator
1/2
PTRST0
Timer 0 reset
PTRST1
Timer 1 reset
Fig. 4.10.6.1 Configuration of 16-bit timer
The registers for timer 0 are used to control the timer. The event counter and PWM output functions can
also be used.
Timer 1 operates with the timer 0 underflow signal as the count clock, so the clock and RUN/STOP
control registers for timer 1 become invalid. However, reload data (PTRSTx) must be preset to timers 0
and 1 separately.
The counter data in 16-bit mode must be read in the order below.
PTD00–PTD03
→ PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17
4.10.7 Interrupt function
The programmable timer can generate an interrupt due to an underflow of each timer or a compare
match of timers 0 and 1. See Figures 4.10.2.1 and 4.10.5.1 for the interrupt timing.
Note: The compare match interrupt can be generated only when timer 0 or 1 is set in PWM mode.
An underflow/compare match of timer x sets the corresponding interrupt factor flag IPTx/ICTCx to "1",
and generates an interrupt. The interrupt can also be masked by setting the corresponding interrupt mask
register EIPTx/ECTCx. However, the interrupt factor flag is set to "1" by an underflow/compare match of
the corresponding timer regardless of the interrupt mask register setting.
When timers 0 and 1 are used as a 16-bit timer, an interrupt is generated by an underflow of timer 1. In
this case, IPT0 is not set to "1" by a timer 0 underflow. The compare match interrupt uses ICTC1 of timer
1.
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