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參數(shù)資料
| 型號(hào)： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁(yè)數(shù)： | 94/121頁(yè) |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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66
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec
or more to count reliably. The noise rejector allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz
signal after changing the input level of the K13 input port terminal.
Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec
or less.
(
: fOSC1 = 32.768 kHz)
Figure 4.10.4.2 shows the count down timing with noise rejector.
Counter
input clock
2
Counter data
n
n-1
n-2
n-3
EVIN input (K13)
2,048 Hz
1
1 When fOSC1 is 32.768 kHz
2 When PLPOL register is set to "0"
Fig. 4.10.4.2 Count down timing with noise rejector
The operation of the event counter mode is the same as the normal timer except it uses the K13 input as
the clock. Refer to Section 4.10.2, "Basic count operation" for basic operation and control.
4.10.5 PWM mode (timer 0, timer 1)
Timer 0 and timer 1 can generate a PWM waveform. When using this function, write "1" to the PTSEL0
register (for timer 0) or PTSEL1 register (for timer 1) to set the timer in the PWM mode.
The compare data register CDx0–CDx7 (x represents a timer number) is provided for timers 0 and 1 to
control the PWM waveform. When the timer is set in the PWM mode, the timer compares data between
the down counter and the compare data register and outputs the compare match signal if their contents
are matched. At the same time a compare match interrupt occurs. Furthermore, the timer output signal
rises with the underflow signal and falls with the compare match signal. As shown in Figure 4.10.5.1, the
cycle and duty ratio of the output signal can be controlled using the reload data register and the compare
data register, respectively, to generate a PWM signal. Note, however, the following condition must be
met: RLD (reload data) > CD (compare data) and CD
≠ 0. If RLD ≤ CD, the output signal is fixed at "1"
after the first underflow occurs and does not fall to "0".
The generated PWM signal can be output from the R02 output port terminal (see Section 4.10.8).
Input clock
RLD register
CD register
Down-counter value
Compare match signal
Underflow signal
Timer output signal
Compare match interrupt
Underflow interrupt
Compare match signal
Underflow signal
Timer output signal
Underflow interrupt
7
6
7
0
6 5 4 3 2 1 0 7 6 5 4
CD register value
3 2 1 0 7 6 5 4 3 2 1
RLD register value + 1
PWM mode
Normal mode
Fig. 4.10.5.1 Generating PWM waveform
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