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EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.13.4.1(b) Control bits of interrupt
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FFF5H
FFF7H
00
IRFB
IRFM
RR/W
0 3
IRFB
IRFM
– 2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Interrupt factor flag (R/f converter reference oscillate completion)
Interrupt factor flag (R/f converter sensor oscillate completion)
IT3
IT2
IT1
IT0
R/W
IT3
IT2
IT1
IT0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 32 Hz)
*1 Initial value at initial reset
*3 Constantly "0" when being read
*2 Not set in the circuit
ECTC1, ECTC0: Interrupt mask registers (FFE0HD1, D0)
EIPT1, EIPT0: Interrupt mask registers (FFE1HD1, D0)
ICTC1, ICTC0: Interrupt factor flags (FFF0HD1, D0)
IPT1, IPT0: Interrupt factor flags (FFF1HD1, D0)
Refer to Section 4.10, "Programmable Timer".
KCP03–KCP00, KCP13–KCP10: Input comparison registers (FF22H, FF26H)
SIK03–SIK00, SIK13–SIK10: Interrupt selection registers (FF20H, FF24H)
EIK0, EIK1: Interrupt mask registers (FFE3HD0, FFE4HD0)
IK0, IK1: Interrupt factor flags (FFF3HD0, FFF4HD0)
Refer to Section 4.5, "Input Ports".
EIT3–EIT0: Interrupt mask registers (FFE5H)
IT3–IT0: Interrupt factor flags (FFF5H)
Refer to Section 4.9, "Clock Timer".
EIRFB, EIRFM: Interrupt mask registers (FFE7HD1, D0)
IRFB, IRFM: Interrupt factor flags (FFF7HD1, D0)
Refer to Section 4.12, "R/f Converter".
4.13.5 Programming notes
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine. Further,
when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all
the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set.