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參數(shù)資料
| 型號： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 7/121頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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96
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (R/f Converter)
EIRFM, EIRFB: Interrupt mask registers (FFE7HD0, D1)
Select whether to mask interrupt with the R/f converter.
When "1" is written: Enable
When "0" is written: Mask
Reading: Valid
EIRFM and EIRFB are the interrupt mask registers for the sensor oscillate completion interrupt and the
reference oscillate completion interrupt. The R/f converter interrupt is permitted when "1" is written to
EIRFM and EIRFB. When "0" is written, interrupt is masked.
At initial reset, these registers are set to "0".
IRFM, IRFB: Interrupt factor flags (FFF7HD0, D1)
These flags indicate the status of the R/f converter interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
IRFB is set to "1" when an R/f conversion for the reference resistor is terminated or when the time base
counter overflows while counting the oscillation of the reference resistance.
IRFM is set to "1" when an R/f conversion for the sensor is terminated or when the measurement counter
overflows while counting the oscillation of the sensor.
From the status of these flags, the software can decide whether an R/f converter interrupt has occurred.
Further this flag is set in the above timing regardless of the interrupt mask register setting (except for
debug mode). These flags are reset to "0" by writing "1". After an interrupt occurs, the same interrupt will
occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the
interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the
interrupt service routine before shifting to the interrupt enabled state.
After an initial reset, these flags are set to "0".
4.12.6 Programming notes
(1) Depending on the initial value of the measurement counter (MC), the measurement counter or the
time base counter may overflow while the CR oscillation clock is being counted. When setting the
initial value, pay attention to CR oscillation frequency, its fluctuation range and the input clock
frequency of the time base counter. If an overflow occurs, R/f conversion is terminated immediately.
When the R/f conversion result (measurement counter value) is read, check the overflow flags
(OVMC and OVTBC). The upper limit of the CR oscillation frequency is 500 kHz. There is no lower-
limit but make sure that the time base counter does not overflow.
(2) When an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag
(OVMC or OVTBC) is not reset. Be sure to check and reset to "0" (writing "1") the overflow flag when
the R/f converter interrupt occurs.
(3) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(4) When selecting OSC3 for the time base counter clock, the maximum frequency of the OSC3 clock is
limited to 2 MHz.
(5) When setting the measurement counter, always write 5 words of data continuously in order from the
lower address (FF92H
→ FF93H → FF94H → FF95H → FF96H). Furthermore, an LD instruction
should be used for writing data to the measurement counter and a read-modify-write instruction
(AND, OR, ADD, SUB, etc.) cannot be used.
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