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參數(shù)資料
| 型號： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 84/121頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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S1C63653 TECHNICAL MANUAL
EPSON
57
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.8.7 I/O memory of LCD driver
Table 4.8.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.8.7.1 shows the
display memory map.
Table 4.8.7.1 Control bits of LCD driver
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF60H
LDUTY1 LDUTY0 STCD
LPWR
R/W
LDUTY1
LDUTY0
STCD
LPWR
0
Static
On
Dynamic
Off
LCD drive duty
switch
LCD drive switch
LCD power On/Off
FF61H
0
ALOFF
ALON
0
RR
R/W
0 3
ALOFF
ALON
0 3
– 2
1
0
– 2
All Off
All On
Normal
Unused
LCD all Off control
LCD all On control
Unused
FF62H
LC3
LC2
LC1
LC0
R/W
LC3
LC2
LC1
LC0
0
Light
–
15
Dark
[LC3–0]
Contrast
LCD contrast adjustment
0
1/4
1
1/5
2
1/6
3
1/3
[LDUTY1, 0]
Duty
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Address
Base
Low
01
234
567
89
A
B
C
D
E
F
F000H
F010H
F020H
Display memory (48 words
× 4 bits)
R/W
Fig. 4.8.7.1 Display memory map
LPWR: LCD power control (on/off) register (FF60HD0)
Turns the LCD system voltage circuit on and off.
When "1" is written: On
When "0" is written: Off
Reading: Valid
When "1" is written to the LPWR register, the LCD system voltage circuit goes on and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to VSS level.
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
This control does not affect to SEG terminals that have been set for DC output.
At initial reset, this register is set to "0".
LDUTY0, LDUTY1: LCD drive duty switching register (FF60HD2, D3)
Selects the LCD drive duty.
Table 4.8.7.2 Drive duty setting
LDUTY1
1
0
LDUTY0
1
0
1
0
Drive duty
1/3
1/6
1/5
1/4
Common terminal used
COM0–COM2
COM0–COM5
COM0–COM4
COM0–COM3
Maximum segment number
96 (32
× 3)
192 (32
× 6)
160 (32
× 5)
128 (32
× 4)
At initial reset, this register is set to "0".
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