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參數(shù)資料
| 型號： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 57/121頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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32
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4.4 Switching of operating voltage
The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). In this case, to
obtain stable operation, the operating voltage for the internal circuits must be switched by the software
(VDC0 register).
When running with the OSC1 clock: Operating clock = VD1L (VDC0 = "0", VDC1 = "0")
When running with the OSC3 clock: Operating clock = VD3
(VDC0 = "1", VDC1 = "1")
The CPU clock should be switched using the following procedure. Pay special attention to the stability
waiting time for operating voltage and oscillation.
Note that the OSC3 clock cannot be used as the system clock in the halver mode. When the low-speed
operation voltage regulator is in the halver mode, return it to the normal mode before switching the
operating voltage.
OSC1
→ OSC3
1. Set VDC2 to "0". (low-speed operation voltage regulator: halver mode
→ normal mode)
2. Set VDC1 to "1". (high-speed operation voltage regulator: off
→ on)
3. Set VDC0 to "1". (internal logic operating voltage: VD1L
→ VD3)
4. Wait 2.5 msec or more.
5. Set OSCC to "1". (OSC3 oscillation: off
→ on)
6. Wait 5 msec or more.
7. Set CLKCHG to "1". (CPU clock: OSC1
→ OSC3)
OSC3
→ OSC1
1. Set CLKCHG to "0". (CPU clock: OSC3
→ OSC1)
2. Set OSCC to "0". (OSC3 oscillation: on
→ off)
3. Set VDC0 to "0". (internal logic operating voltage: VD3
→ VD1L)
4. Set the halver mode if necessary.
Refer to Section 4.2, "Power Control", for the halver mode.
Note: If the HALT instruction is executed or HALT mode is canceled while the CPU is running with the
high-speed clock generated by the OSC3 oscillation circuit, the internal logic operating voltage VD1
becomes unstable momentarily and it may cause unexpected problem, such as runaway, be
occurred. Do not use the HALT instruction while the CPU is running with the OSC3 high-speed
clock.
4.4.5 Clock frequency and instruction execution time
Table 4.4.5.1 shows the instruction execution time according to each frequency of the system clock.
Table 4.4.5.1 Clock frequency and instruction execution time
Clock frequency
OSC1: 32.768 kHz
OSC3: 1.1 MHz
OSC3: 2 MHz
OSC3: 4 MHz
Instruction execution time (
sec)
1-cycle instruction
2-cycle instruction
3-cycle instruction
61
122
183
1.8
3.6
5.5
123
0.5
1
1.5
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