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參數(shù)資料
| 型號(hào)： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 92/121頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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64
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.2 Basic count operation
This section explains the basic count operation when each timer is used as an individual 8-bit timer.
Each timer has an 8-bit down counter and an 8-bit reload data register.
The reload data register RLDx0–RLDx7 (x = timer number) is used to set the initial value to the down
counter.
By writing "1" to the timer reset bit PTRSTx, the down counter loads the initial value set in the reload
register. Therefore, down-counting is executed from the stored initial value by the input clock.
The PTRUNx register is provided to control the RUN/STOP for each timer. By writing "1" to this register
after presetting the reload data to the down counter, the down counter starts counting down. Writing "0"
stops the input count clock and the down counter stops counting. This control (RUN/STOP) does not
affect the counter data. The counter maintains its data while stopped, and can restart counting continuing
from that data.
The counter data can be read via the data buffer PTDx0–PTDx7 in optional timing. However, the counter
has the data hold function the same as the clock timer, that holds the high-order data (PTDx4–PTDx7)
when the low-order data (PTDx0–PTDx3) is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register when an underflow occurs through the
count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation and pulse
(TOUT signal) output.
PTRUNx
PTRSTx
RLDx0–x7
Input clock
PTDx7
PTDx6
PTDx5
PTDx4
PTDx3
PTDx2
PTDx1
PTDx0
A6H
F3H
Preset
Reload &
underflow interrupt
Fig. 4.10.2.1 Basic operation timing of down counter
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