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參數(shù)資料
| 型號： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 73/121頁 |
| 文件大小： | 1127K |
| 代理商： | S1C63653F |
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S1C63653 TECHNICAL MANUAL
EPSON
47
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
When reading data
When "1" is read: High level
When "0" is read: Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the register value can be read.
When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal
voltage is low (VSS) the data is "0".
When "with pull-down resistor" has been selected with the mask option and the PUL register is set to "1",
the built-in pull-down resistor goes on during input mode, so that the I/O port terminal is pulled down.
Note: When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of
the waveform is delayed on account of the time constant of the pull-down resistor and input gate
capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k
(Max.)
IOC00–IOC03: P0 port I/O control register (FF40H)
IOC10–IOC13: P1 port I/O control register (FF44H)
The input and output modes of the I/O ports are set with these registers.
When "1" is written: Output mode
When "0" is written: Input mode
Reading: Valid
The input and output modes of the I/O ports are set in 1-bit unit.
Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and
writing "0" induces the input mode.
At initial reset, these registers are all set to "0", so the I/O ports are in the input mode.
PUL00–PUL03: P0 port pull-down control register (FF41H)
PUL10–PUL13: P1 port pull-down control register (FF45H)
The pull-down during the input mode are set with these registers.
When "1" is written: Pull-down On
When "0" is written: Pull-down Off
Reading: Valid
The built-in pull-down resistor which is turned on during input mode is set to enable in 1-bit units. (The
pull-down resistor is included into the ports selected by mask option.)
By writing "1" to the pull-down control register, the corresponding I/O ports are pulled down (during
input mode), while writing "0" disables the pull-down function.
At initial reset, these registers are all set to "1", so the pull-down function is enabled.
The pull-down control registers of the ports in which the pull-down resistor is not included become the
general purpose register.
4.7.6 Programming note
When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of the
waveform is delayed on account of the time constant of the pull-down resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k
(Max.)
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