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參數(shù)資料
| 型號(hào)： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 16/121頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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104
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
5.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mind when
programming.
Memory and stack
(1)Memory is not implemented in unused areas within the memory map. Further, some non-implemen-
tation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the program that
accesses these areas is generated, its operation cannot be guaranteed. Refer to the I/O memory maps
shown in Table 4.1.1 for the peripheral I/O area.
(2) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(3) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63653 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts
including NMI are masked until both the stack pointers SP1 and SP2 are set by software. Further, if
either SP1 or SP2 is re-set when both are set already, the interrupts including NMI are masked again
until the other is re-set. Therefore, the settings of SP1 and SP2 must be done as a pair.
Power control
(1) When setting the low-speed operation voltage regulator into the halver mode, switch the CPU clock to
OSC1 before writing "1" to VDC2.
(2) When setting the LCD system voltage circuit into the halver mode, set the VC1 voltage (contrast) to
1.13 V or lower (LC register = 6 or less) before writing "1" to VDC3.
Watchdog timer
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
Oscillation circuit
(1) When switching the CPU system clock from OSC1 to OSC3, first set the operating voltage for high-
speed operation (VD3). After that maintain 2.5 msec or more, and then turn the OSC3 oscillation on.
When switching from OSC3 to OSC1, set the operating voltage for low-speed operation (VD1L) after
switching to OSC1 and turning the OSC3 oscillation off.
(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went on.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation off. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(4) When the low-speed operation voltage regulator is in the halver mode (VDC2 = "1"), the system can
be operated only in low-speed using the OSC1 clock. Do not switch the system clock to OSC3.
(5) Do not switch the operating voltage to VD1L while the CPU is operating with the OSC3 clock. Further-
more, do not stop the high-speed operating voltage regulator.
(6) When selecting OSC3 for the time base counter clock of the R/f converter, the maximum frequency of
the OSC3 clock is limited to 2 MHz.
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