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EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4.7 Programming notes
(1) When switching the CPU system clock from OSC1 to OSC3, first set the operating voltage for high-
speed operation (VD3). After that maintain 2.5 msec or more, and then turn the OSC3 oscillation on.
When switching from OSC3 to OSC1, set the operating voltage for low-speed operation (VD1L) after
switching to OSC1 and turning the OSC3 oscillation off.
(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went on.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation off. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(4) When the low-speed operation voltage regulator is in the halver mode (VDC2 = "1"), the system can
be operated only in low-speed using the OSC1 clock. Do not switch the system clock to OSC3.
(5) Do not switch the operating voltage to VD1L while the CPU is operating with the OSC3 clock. Further-
more, do not stop the high-speed operating voltage regulator.
(6) When selecting OSC3 for the time base counter clock of the R/f converter, the maximum frequency of
the OSC3 clock is limited to 2 MHz.
(7) If the HALT instruction is executed or HALT mode is canceled while the CPU is running with the
high-speed clock generated by the OSC3 oscillation circuit, the internal logic operating voltage VD1
becomes unstable momentarily and it may cause unexpected problem, such as runaway, be occurred.
Do not use the HALT instruction while the CPU is running with the OSC3 high-speed clock.