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| 型號(hào)： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁(yè)數(shù)： | 18/121頁(yè) |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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106
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the
PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1).
The PTRUNx register maintains "1" for reading until the timer actually stops.
Figure 5.2.1 shows the timing chart for the RUN/STOP control.
PTRUNx (WR)
PTDx0–PTDx7
42H
41H 40H 3FH 3EH
3DH
PTRUNx (RD)
Input clock
"1" (RUN)
writing
"0" (STOP)
writing
Fig. 5.2.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned on and off by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the off state.
(5) For the reason below, pay attention to the reload data write timing when changing the interval of the
programmable timer interrupts while the programmable timer is running.
The programmable timer counts down at the falling edge of the input clock and at the same time it
generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter
and the counter data is determined at the next rising edge of the input clock (period shown in as in
the figure).
Input clock
Counter data
(continuous mode)
(Reload data = 25H)
03H
02H
01H
00H
25H
24H
Counter data is determined by reloading.
Underflow (interrupt is generated)
Fig. 5.2.2 Reload timing for programmable timer
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period . Be especially careful when using the OSC1 (low-
speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3
(high-speed clock).
Sound generator
(1) Since it generates a buzzer signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes on/off due to the setting of the BZE register.
(2) The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid
when the normal buzzer output is on (BZE = "1").
R/f converter
(1) Depending on the initial value of the measurement counter (MC), the measurement counter or the
time base counter may overflow while the CR oscillation clock is being counted. When setting the
initial value, pay attention to CR oscillation frequency, its fluctuation range and the input clock
frequency of the time base counter. If an overflow occurs, R/f conversion is terminated immediately.
When the R/f conversion result (measurement counter value) is read, check the overflow flags
(OVMC and OVTBC). The upper limit of the CR oscillation frequency is 500 kHz. There is no lower-
limit but make sure that the time base counter does not overflow.
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