參數(shù)資料
型號： S1C63653F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100
封裝： CERAMIC, QFP15-100
文件頁數(shù)： 48/121頁
文件大?。?/td> 1127K
代理商： S1C63653F
24
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control)
Voltage halver
The voltage halver generates VD2 by halving the supply voltage VDD. Using this halved supply
voltage to drive the low-speed operation voltage regulator and LCD system voltage circuit reduces
current consumption during HALT or low-speed operation. This status is the halver mode and the
VDC2 register is used to set the low-speed operation voltage regulator into the halver mode and the
VDC3 register is used to set the LCD system voltage circuit. However, the supply voltage must be 2.4
V or more to set the halver mode. Furthermore, the halver mode cannot be set during high-speed
operation using the OSC3 clock.
In the normal mode, the low-speed operation voltage regulator and LCD system voltage circuit
operate with the supply voltage VDD directly.
At initial reset, the normal mode is set by hardware.
The voltage halver always operates regardless of the mode set.
4.2.2 Power control procedure
At initial reset, the power supply, operating voltage and oscillation circuit are set as follows:
Low-speed operation voltage regulator: ON
Normal mode (VDC2 = "0")
LCD system voltage circuit:
OFF
(LPWR = "0")
Normal mode (VDC3 = "0")
High-speed operation voltage regulator: OFF
(VDC1 = "0")
CPU/internal logic operating voltage:
VD1L
(VDC0 = "0")
CPU system clock:
OSC1
(CLKCHG = "0")
OSC3 oscillation circuit:
OFF
(OSCC = "0")
Setting halver mode
The low-speed operation voltage regulator and the LCD system voltage circuit can be set into the
halver mode independently.
Setting the low-speed operation voltage regulator
The low-speed operation voltage regulator can be set into the halver mode under the conditions
below.
When the supply voltage VDD is 2.4 V or higher.
When the CPU/internal circuits operate with the VD1L operating voltage and OSC1 operating clock.
The following shows the switching procedure from normal mode to halver mode.
1. Switch the CPU clock from OSC3 to OSC1 (CLKCHG = "0", when OSC3 is used as the CPU clock)
2. Stop the OSC3 oscillation (OSCC = "0")
3. Switch the internal operating voltage from VD3 to VD1L (VDC0 = "0")
4. Turn the high-speed operation voltage circuit off (VDC1 = "0")
5. Set the halver mode (VDC2 = "1")
Steps 1 to 4 are necessary during high-speed operation.
Setting the LCD system voltage circuit
The LCD system voltage circuit can be set into the halver mode under the conditions below.
When the supply voltage VDD is 2.4 V or higher.
When the VC1 setup value for driving the LCD is 1.13 V or lower.
The following shows the switching procedure.
1. Set the LCD drive voltage VC1 to 1.13 V or lower (LC3–LC0
≤ 6)
2. Set the halver mode (VDC3 = "1")
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