參數(shù)資料
型號： S1C63653F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100
封裝： CERAMIC, QFP15-100
文件頁數(shù)： 50/121頁
文件大小： 1127K
代理商： S1C63653F
26
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control)
VDC1: High-speed operation voltage regulator control (ON/OFF) register (FF00HD1)
Turns the high-speed operation voltage regulator on and off.
When "1" is written: On
When "0" is written: Off
Reading: Valid
When "1" is written to VDC1, the high-speed operation voltage regulator goes to generate the high-speed
operation voltage VD3 for the internal logic circuits.
When "0" is written to VDC1, the high-speed operation voltage regulator stops operating. Do not write
"0" to VDC1 while the CPU is operating with the OSC3 clock.
At initial reset, this register is set to "0".
VDC2: Low-speed operation voltage regulator power control register (FF00HD2)
Sets the low-speed operation voltage regulator to the halver mode.
When "1" is written: Halver mode (driven with 1/2 VDD)
When "0" is written: Normal mode (driven with VDD)
Reading: Valid
When "1" is written to VDC2, the low-speed operation voltage regulator enters the halver mode. In this
mode, the low-speed operation voltage regulator operates with 1/2 the VDD voltage, this makes it
possible to reduce current consumption. However, the supply voltage VDD must be 2.4 V or higher.
Furthermore, this mode does not allow high-speed operation using the OSC3 clock.
When "0" is written to VDC2, the low-speed operation voltage regulator enters the normal mode and
operates with the supply voltage VDD.
At initial reset, the hardware sets the normal mode and this register is set to "0".
VDC3: LCD system voltage circuit power control register (FF00HD3)
Sets the LCD system voltage circuit to the halver mode.
When "1" is written: Halver mode (driven with 1/2 VDD)
When "0" is written: Normal mode (driven with VDD)
Reading: Valid
When "1" is written to VDC3, the LCD system voltage circuit enters the halver mode. In this mode, the
LCD system voltage circuit operates with 1/2 the VDD voltage, this makes it possible to reduce current
consumption. However, the supply voltage VDD must be 2.4 V or higher and the VC1 setup voltage must
be 1.13 V or lower. Furthermore, this mode does not allow high-speed operation using the OSC3 clock.
When "0" is written to VDC3, the LCD system voltage circuit enters the normal mode and operates with
the supply voltage VDD.
At initial reset, the hardware sets the normal mode and this register is set to "0".
LPWR: LCD power control (ON/OFF) register (FF60HD0)
Turns the LCD system voltage circuit on and off.
When "1" is written: On
When "0" is written: Off
Reading: Valid
When "1" is written to the LPWR register, the LCD system voltage circuit goes on and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to VSS level.
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
At initial reset, this register is set to "0".
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