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參數(shù)資料
| 型號： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 17/121頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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S1C63653 TECHNICAL MANUAL
EPSON
105
CHAPTER 5: SUMMARY OF NOTES
(7) If the HALT instruction is executed or HALT mode is canceled while the CPU is running with the
high-speed clock generated by the OSC3 oscillation circuit, the internal logic operating voltage VD1
becomes unstable momentarily and it may cause unexpected problem, such as runaway, be occurred.
Do not use the HALT instruction while the CPU is running with the OSC3 high-speed clock.
Input port
When input ports are changed from high to low by pull-down resistors, the fall of the waveform is
delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time. Particular care needs to be taken of the
key scan during key matrix configuration. Make this waiting time the amount of time or more calcu-
lated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k
(Max.)
Output port
(1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output). Be aware that the
output terminal is fixed at a low (VSS) level the same as the DC output if "0" is written to the R02 and
R03 registers when the special output has been selected. Be aware that the output terminal shifts into
high impedance status when "1" is written to the high impedance control register (R02HIZ, R03HIZ).
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned on and off.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output. Refer to Section 4.4, "Oscillation Circuit", for the control and notes.
I/O port
When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of the
waveform is delayed on account of the time constant of the pull-down resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k
(Max.)
LCD driver
Because at initial reset, the contents of display memory are undefined and LC3–LC0 (LCD contrast) is
set to 0000B, there is need to initialize by the software. Furthermore, take care of the registers LPWR
and ALOFF because these are set so that the display goes off.
Clock timer
Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–
TM7).
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. Furthermore,
the high-order 4 bits (PTDx4–PTDx7) are not latched when the low-order 4 bits are read. Therefore,
the high-order 4 bits should be read within 0.73 msec (when fOSC1 is 32.768 kHz) from reading the
low-order 4 bits. When the CPU is running with the OSC1 clock and the programmable timer is
running with the OSC3 clock, stop the timer before reading the counter data. The counter running
with OSC3 counts down for the value listed in Table 5.2.1 while the CPU running with OSC1 reads the
low-order 4 bits and high-order 4 bits of the counter data by two instructions.
Table 5.2.1 Counter change with OSC3 between readings low-order and high-order data with OSC1
Count clock
OSC3/1
OSC3/4
OSC3/32
Counter change between reading
0200H
001AH
0002H
In 16-bit mode, the counter data must be read in the order below.
PTD00–PTD03
→ PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17
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