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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 91/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
81
August 22, 2002 – Revision 1.02
1:0
Power State
R/W
Indicates the current power state of PI7C8150. If an unimplemented
power state is written to this register, PI7C8150 completes the write
transaction, ignores the write data, and does not change the value of
the field. Writing a value of D0 when the previous state was D3
cause a chip reset without asserting S_RESET_L
00: D0 state
01: not implemented
10: not implemented
11: D3 state
Reset to 0
Read as 0
Read as 0 as PI7C8150 does not support the PME# pin.
Read as 0 as the data register is not implemented.
Read as 0 as the data register is not implemented.
Read as 0 as the PME# pin is not implemented.
7:2
8
12:9
14:13
15
Reserved
PME# Enable
Data Select
Data Scale
PME status
R/O
R/O
R/O
R/O
R/O
14.1.54
CAPABILITY ID REGISTER – OFFSET E4h
Bit
Function
Type
Description
00h: Reserved.
7:0
Capability ID
R/O
01h: PCI Power Management (PCIPM)
02h: Accelerated Graphics Port (AGP)
03h: Vital Product Data (VPD)
04h: Slot Identification (SI)
05h: Message Signaled Interrupts (MSI)
06h: Compact PCI Hot Swap
07h-255h: Reserved
14.1.55
NEXT POINTER REGISTER – OFFSET E4h
Bit
15:8
Function
Next Pointer
Type
R/O
Description
End of pointer (00h)
15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number
of possibilities. Those possibilities are summarized in the table below:
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator
Master on Primary
Target
Target on Primary
Response
PI7C8150 does not respond. It detects
this situation by decoding the address as
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