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參數(shù)資料
| 型號(hào)： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 53/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
43
August 22, 2002 – Revision 1.02
PI7C8150 completes the transaction normally.
6.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8150 responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
PI7C8150 asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C8150 sets the parity error detected bit in the status register of the primary
interface.
PI7C8150 captures and forwards the bad parity condition to the secondary bus.
PI7C8150 completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C8150 responds as a target,
it detects a data parity error on the initiator (secondary) bus, the following events occur:
PI7C8150 asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C8150 sets the parity error detected bit in the status register of the secondary
interface.
PI7C8150 captures and forwards the bad parity condition to the primary bus.
PI7C8150 completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
PI7C8150 sets the data parity detected bit in the status register of secondary interface,
if the parity error response bit is set in the bridge control register of the secondary
interface.
PI7C8150 asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
The SERR_L enable bit is set in the command register.
The posted write parity error bit of P_SERR_L event disable register is not
set.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
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