參數(shù)資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 66/106頁
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
56
August 22, 2002 – Revision 1.02
Write-1-to-set output data field
Write-1-to-clear output data field
Write-1-to-set signal output enable control field
Write-1-to-clear signal output enable control field
Input data field
The bottom four bits of the output enable fields control whether each GPIO signal is input
only or bi-directional. Each signal is controlled independently by a bit in each output
enable control field. If a 1 is written to the write-1-to-set field, the corresponding pin is
activated as an output. If a 1 is written to the write-1-to-clear field, the output driver is tri-
stated, and the pin is then input only. Writing zeroes to these registers has no effect. The
reset for these signals is input only.
The input data field is read only and reflects the current value of the GPIO pins. A type 0
configuration read operation to this address is used to obtain the values of these pins. All
pins can be read at any time, whether configured as input only or as bi-directional.
The output data fields also use the write-1-to-set and write-1-to-clear mode. If a 1 is
written to the write-1-to-set field and the pin is enabled as an output, the corresponding
GPIO output is driven HIGH. If a 1 is written to the write-1-to-clear field and the pin is
enabled as an output, the corresponding GPIO output is driven LOW. Writing zeros to
these registers has no effect. The value written to the output register will be driven only
when the GPIO signal is configured as bi-directional. A type 0 configuration write
operation is used to program these fields. The rest value for the output is 0.
10.2
SECONDARY CLOCK CONTROL
The PI7C8150 uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data
stream. This data stream is shifted into the secondary clock control register and is used for
selectively disabling secondary clock outputs.
The serial data stream is shifted in as soon as P_RST_L is detected deasserted and the
secondary reset signal, S_RST_L, is detected asserted. The deassertion of S_RST_L is
delayed until the PI7C8150 completes shifting in the clock mask data, which takes 23 clock
cycles. After that, the GPIO pins can be used as general-purpose I/O pins.
An external shift register should be used to load and shift the data. The GPIO pins are used
for shift register control and serial data input. Table 11-1
shows the operation of the GPIO
pins.
Table 11-1. GPIO Operation
GPIO Pin
Operation
GPIO[0]
GPIO[1]
GPIO[2]
Shift register clock output at 33MHz max frequency
Not used
Shift register control
0: Load
1: Shift
Not used
GPIO[3]
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