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參數(shù)資料
| 型號(hào)： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 39/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
29
August 22, 2002 – Revision 1.02
3.8.4.3
TARGET ABORT
PI7C8150 returns a target abort to an initiator when one of the following conditions is met:
PI7C8150 is returning a target abort from the intended target.
When PI7C8150 returns a target abort to the initiator, it sets the signaled target abort
bit in the status register corresponding to the initiator interface.
4
ADDRESS DECODING
PI7C8150 uses three address ranges that control I/O and memory transaction forwarding.
These address ranges are defined by base and limit address registers in the configuration
space. This chapter describes these address ranges, as well as ISA-mode and VGA-
addressing support.
4.1
ADDRESS RANGES
PI7C8150 uses the following address ranges that determine which I/O and memory
transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from
the secondary bus to the primary bus:
Two 32-bit I/O address ranges
Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges
Two 32-bit prefetchable memory address ranges
Transactions falling within these ranges are forwarded downstream from the primary PCI
bus to the secondary PCI bus. Transactions falling outside these ranges are forwarded
upstream from the secondary PCI bus to the primary PCI bus.
No address translation is required in PI7C8150. The addresses that are not marked for
downstream are always forwarded upstream.
4.2
I/O ADDRESS DECODING
PI7C8150 uses the following mechanisms that are defined in the configuration space to
specify the I/O address space for downstream and upstream forwarding:
I/O base and limit address registers
The ISA enable bit
The VGA mode bit
The VGA snoop bit
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