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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 81/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
71
August 22, 2002 – Revision 1.02
18
ISA enable
R/W
Modifies the bridge’s response to ISA I/O addresses, applying only
to those addresses falling within the I/O base and limit address
registers and within the first 64KB or PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the
last 768 bytes in each 1KB block
Reset to 0
Controls the bridge’s response to VGA compatible addresses.
19
VGA enable
R/W
0: does not forward VGA compatible memory and I/O
addresses from primary to secondary
1: forward VGA compatible memory and I/O addresses from
primary to secondary regardless of other settings
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Control’s bridge’s behavior responding to master aborts on
secondary interface.
20
21
Reserved
Master Abort
Mode
R/O
R/W
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible by the
assertion of P_SERR_L if enabled
Reset to 0
Controls the assertion of S_RESET_L signal pin on the secondary
interface
22
Secondary
Interface Reset
R/W
0: does not force the assertion of S_RESET_L pin
1: forces the assertion of S_RESET_L
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
23
Fast Back-to-
Back Enable
R/W
0: does not allow fast back-to-back transactions
1: enables fast back-to-back transactions
Reset to 0
Reserved. Reset to 0
Reserved. Reset to 0
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
24
25
26
Reserved
Reserved
Master Timeout
Status
R/W
R/W
R/WC
Reset to 0
This bit is set to 1 and P_SERR_L is asserted when either the
primary discard timer or the secondary discard timer expire.
27
Discard Timer
P_SERR_L
enable
R/W
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
31-28
Reserved
R/O
14.1.29
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
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