參數(shù)資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 50/106頁
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
40
August 22, 2002 – Revision 1.02
PI7C8150 asserts S_PERR_L two cycles following the data transfer, if the secondary
interface parity error response bit is set in the bridge control register.
PI7C8150 sets the detected parity error bit in the secondary status register.
PI7C8150 sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
PI7C8150 forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
primary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150 completes the transaction normally.
For upstream transactions, when PI7C8150 detects a read data parity error on the primary
bus, the following events occur:
PI7C8150 asserts P_PERR_L two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
PI7C8150 sets the detected parity error bit in the primary status register.
PI7C8150 sets the data parity detected bit in the primary status register, if the primary
interface parity-error-response bit is set in the command register.
PI7C8150 forwards the bad parity with the data back to the initiator on the secondary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
secondary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150 completes the transaction normally.
PI7C8150 returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C8150 detects PERR_L asserted while returning read data to the initiator, PI7C8150
does not take any further action and completes the transaction normally.
6.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8150 detects a data parity error during a delayed write transaction, the initiator
drives data and data parity, and the target checks parity and conditionally asserts PERR_L.
For delayed write transactions, a parity error can occur at the following times:
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
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