參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 37/106頁(yè)
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
27
August 22, 2002 – Revision 1.02
PI7C8150 receives a target abort.
PI7C8150 makes 2
24
(default) read attempts resulting in a response of target retry.
Table 4-9. Response to Delayed Read Target Termination
Target Termination
Normal
Response
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Re-initiate read transaction to target
If initiator requests more data than read from target, return target disconnect to
initiator.
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
Target Retry
Target Disconnect
Target Abort
After PI7C8150 makes 2
24
(default) attempts of the same delayed read transaction on the
target bus, PI7C8150 asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of
command register for secondary bus) and the delayed-write-non-delivery bit is not set. The
delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).
PI7C8150 will report system error. See Section 7.4 for a description of system error
conditions.
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150
PI7C8150 can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
3.8.4.1
TARGET RETRY
PI7C8150 returns a target retry to the initiator when it cannot accept write data or return
read data as a result of internal conditions. PI7C8150 returns a target retry to an initiator
when any of the following conditions is met:
For delayed write transactions:
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target
response has not yet been received.
Target response has been received but has not progressed to the head of the return
queue.
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across PI7C8150, and the write transaction is
not a locked transaction.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
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