參數(shù)資料
型號(hào): PERICOMPI7C8150
廠商: Pericom Semiconductor Corp.
英文描述: 2-Port PCI-to-PCI Bridge
中文描述: 2端口PCI至PCI橋
文件頁(yè)數(shù): 38/106頁(yè)
文件大?。?/td> 904K
代理商: PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
28
August 22, 2002 – Revision 1.02
For delayed read transactions:
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a
posted write transaction precedes it.
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been
queued.
A locked sequence is being propagated across PI7C8150, and the read transaction is
not a locked transaction.
PI7C78150 is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
For posted write transactions:
The posted write data buffer does not have enough space for address and at least one
DWORD of write data.
A locked sequence is being propagated across PI7C8150, and the write transaction is
not a locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator
must repeat the transaction with the same address and bus command as well as the data
if it is a write transaction, within the time frame specified by the master timeout value.
Otherwise, the transaction is discarded from the buffers.
3.8.4.2
TARGET DISCONNECT
PI7C8150 returns a target disconnect to an initiator when one of the following conditions is
met:
PI7C8150 hits an internal address boundary.
PI7C8150 cannot accept any more write data.
PI7C8150 has no more read data to deliver.
See Section 4.5.4 for a description of write address boundaries, and Section 4.6.3 for a
description of read address boundaries.
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