參數(shù)資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 84/106頁
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
74
August 22, 2002 – Revision 1.02
31:28
Secondary bus
arbiter
preemption
contorl
R/W
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles after FRAME asserted
0001: Preemption enabled after 1 clock cycle after FRAME asserted
0010: Preemption enabled after 2 clock cycles after FRAME asserted
0011: Preemption enabled after 4 clock cycles after FRAME asserted
0100: Preemption enabled after 8 clock cycles after FRAME asserted
0101: Preemption enabled after 16 clock cycles after FRAME
asserted
0110: Preemption enabled after 32 clock cycles after FRAME
asserted
0111: Preemption enabled after 64 clock cycles after FRAME
asserted
14.1.34
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h
Bit
Function
Type
Description
0: 32 bit addressing
3:0
64 bit addressing
R/O
1: 64 bit addressing
Reset to 1
Controls upstream memory base address.
15:4
Upstream
Memory Base
Address
R/W
Reset to 00000000h
14.1.35
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h
Bit
Function
Type
Description
0: 32 bit addressing
19:16
64 bit addressing
R/O
1: 64 bit addressing
Reset to 1
Controls upstream memory limit address.
31:20
Upstream
Memory Limit
Address
R/W
Reset to 000FFFFFh
14.1.36
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER
– OFFSET 54h
Bit
Function
Upstream
Memory Base
Address
Type
Description
Defines bits [63:32] of the upstream memory base
31:0
R/W
Reset to 0
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