參數(shù)資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 7/106頁
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
vii
August 22, 2002 – Revision 1.02
14.1.43
14.1.44
14.1.45
14.1.46
14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
RETRY COUNTER REGISTER – OFFSET 78h
.......................................................... 78
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h
..................................... 79
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h
............................... 79
CAPABILITY ID REGISTER – OFFSET B0h
............................................................. 79
NEXT POINTER REGISTER – OFFSET B0h
............................................................. 79
SLOT NUMBER REGISTER – OFFSET B0h
.............................................................. 79
CHASSIS NUMBER REGISTER – OFFSET B0h
....................................................... 80
CAPABILITY ID REGISTER – OFFSET DCh
............................................................. 80
NEXT ITEM POINTER REGISTER – OFFSET DCh
................................................. 80
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh
................. 80
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
................................... 80
CAPABILITY ID REGISTER – OFFSET E4h
............................................................. 81
NEXT POINTER REGISTER – OFFSET E4h
............................................................. 81
15
BRIDGE BEHAVIOR.................................................................................................................... 81
15.1
15.2
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES .............................................................. 81
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER).................................... 82
15.2.1
MASTER ABORT
................................................................................................................ 82
15.2.2
PARITY AND ERROR REPORTING
................................................................................ 82
15.2.3
REPORTING PARITY ERRORS
....................................................................................... 82
15.2.4
SECONDARY IDSEL MAPPING
...................................................................................... 83
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 83
16.1
BOUNDARY SCAN ARCHITECTURE..................................................................................... 83
16.1.1
TAP PINS
............................................................................................................................. 84
16.1.2
INSTRUCTION REGISTER
............................................................................................... 84
16.2
BOUNDARY SCAN INSTRUCTION SET ................................................................................ 85
16.3
TAP TEST DATA REGISTERS.................................................................................................. 85
16.4
BYPASS REGISTER................................................................................................................... 86
16.5
BOUNDARY-SCAN REGISTER................................................................................................ 86
16.6
TAP CONTROLLER................................................................................................................... 86
17
ELECTRICAL AND TIMING SPECIFICATIONS................................................................... 90
17.1
17.2
17.3
17.4
17.5
17.6
MAXIMUM RATINGS............................................................................................................... 90
DC SPECIFICATIONS................................................................................................................ 90
AC SPECIFICATIONS................................................................................................................ 91
66MHZ TIMING.......................................................................................................................... 91
33MHZ TIMING.......................................................................................................................... 92
POWER CONSUMPTION .......................................................................................................... 92
18
PACKAGE INFORMATION........................................................................................................ 92
18.1
18.2
18.3
208-PIN FQFP PACKAGE DIAGRAM...................................................................................... 92
256-BALL PBGA PACKAGE DIAGRAM................................................................................. 93
PART NUMBER ORDERING INFORMATION........................................................................ 93
LIST OF TABLES
Table 3-1. Pin list – 208-pin FQFP
_______________________________________________________ 7
Table 3-2. Pin list – 208-pin FQFP
_______________________________________________________ 9
Table 4-1. PCI Transactions
___________________________________________________________ 11
Table 4-2. Write Transaction Forwarding
________________________________________________ 12
Table 4-3. Write Transaction Disconnect Address Boundaries
________________________________ 15
Table 4-4. Read Prefetch Address Boundaries
_____________________________________________ 16
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