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參數(shù)資料
| 型號(hào)： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 72/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
62
August 22, 2002 – Revision 1.02
1011
Configuration Write
I. Type 0 Configuration Write: Ignore
II. Type 1 Configuration Write (not special cycle
request):Ignore
III. Configuration Write as Special Cycle Request (device
= 1Fh, function = 7h):
1. If the target bus is the bridge’s primary bus: claim and
pass through as a Special Cycle
2. If the target bus is neither the primary bus nor is it in range
of buses defined by the bridge’s secondary and subordinate
bus registers: claim and pass through unchanged as a Type 1
Configuration Write.
3. If the target bus is not the bridge’s primary bus, but is in
range of buses defined by the bridge’s secondary and
subordinate bus registers: ignore.
Same as Memory Read
1100
Memory Read
Multiple
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate
1101
1110
1111
Supported
Same as Memory Read
Same as Memory Read
14
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte space (configuration header) to define various
attributes of PI7C8150 as shown below.
14.1
CONFIGURATION REGISTER
31-24
23-16
15-8
7-0
Address
00h
04h
08h
0Ch
10h
14h
18h
Device ID
Primary Status
Vendor ID
Command
Class Code
Header Type
Revision ID
Cache Line Size
Reserved
Primary Latency Timer
Reserved
Reserved
Secondary Bus
Number
I/O Limit
Secondary Latency
Timer
Subordinate Bus
Number
Primary Bus Number
Secondary Status
Memory Limit
Prefetchable Memory Limit
I/O Base
1Ch
20h
24h
28h
2Ch
30h
34h
Memory Base
Prefetchable Memory Base
Prefetchable Base Upper 32-bit
Prefetchable Limit Upper 32-bit
I/O Limit Upper 16-bit
I/O Base Upper 16-bit
Reserved
Capability Pointer to
DCh
Reserved
38h
3Ch
40h
44h
48h
4Ch
Bridge Control
Arbiter Control
Reserved
Interrupt Line
Diagnostic / Chip Control
Reserved
Upstream Memory Control
Extended Chip Control
Secondary
Bus Arbiter
Preemption
Control
Hot Swap Switch Time Slot
Upstream (S to P) Memory Limit
Upstream (S to P) Memory Base
50h
54h
Upstream (S to P) Memory Base Upper 32-bit
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