參數(shù)資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 21/106頁
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
11
August 22, 2002 – Revision 1.02
This section provides a summary of PCI transactions performed by PI7C8150.
Table 4–1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C8150 initiates transactions
as a master, on the primary (P) and secondary (S) buses, and when PI7C8150 responds to
transactions as a target, on the primary (P) and secondary (S) buses.
Table 4-1. PCI Transactions
Types of Transactions
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Secondary
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
As indicated in Table 4–1, the following PCI commands are not supported by PI7C8150:
PI7C8150 never initiates a PCI transaction with a reserved command code and, as a
target, PI7C8150 ignores reserved command codes.
PI7C8150 does not generate interrupt acknowledge transactions. PI7C8150 ignores
interrupt acknowledge transactions as a target.
PI7C8150 does not respond to special cycle transactions. PI7C8150 cannot guarantee
delivery of a special cycle transaction to downstream buses because of the broadcast
nature of the special cycle command and the inability to control the transaction as a
target. To generate special cycle transactions on other PCI buses, either upstream or
downstream, Type 1 configuration write must be used.
PI7C8150 neither generates Type 0 configuration transactions on the primary PCI
bus nor responds to Type 0 configuration transactions on the secondary PCI buses.
3.2
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and
the bus command is driven on P_CBE[3:0]. PI7C8150 supports the linear increment
address mode only, which is indicated when the lowest two address bits are equal to zero.
If either of the lowest two address bits is nonzero, PI7C8150 automatically disconnects the
transaction after the first data transfer.
3.3
DEVICE SELECT (DEVSEL_L) GENERATION
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