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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 77/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
67
August 22, 2002 – Revision 1.02
Bit
31:24
Function
Secondary
Latency Timer
Type
R/W
Description
Designated in units of PCI bus clocks. Latency timer checks for
master accesses on the secondary bus interfaces that remain
unclaimed by any target.
Reset to 0
14.1.14
I/O BASE REGISTER – OFFSET 1Ch
Bit
3:0
7:4
Function
32-bit Indicator
I/O Base Address
[15:12]
Type
R/O
R/W
Description
Read as 01h to indicate 32-bit I/O addressing
Defines the bottom address of the I/O address range for the bridge
to determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be 0. The upper 16 bits corresponding to address
bits [31:16] are defined in the I/O base address upper 16 bits address
register
Reset to 0
14.1.15
I/O LIMIT REGISTER – OFFSET 1Ch
Bit
11:8
15:12
Function
32-bit Indicator
I/O Base Address
[15:12]
Type
R/O
R/W
Description
Read as 01h to indicate 32-bit I/O addressing
Defines the top address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be FFFh. The upper 16 bits corresponding to
address bits [31:16] are defined in the I/O base address upper 16 bits
address register
Reset to 0
14.1.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
20:16
21
Function
Reserved
66MHz Capable
Type
R/O
R/O
Description
Reset to 0
Set to 1 to enable 66MHz operation on the secondary interface
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the
secondary interface to different targets
22
Reserved
R/O
23
Fast Back-to-
Back Capable
R/O
Reset to 0
Set to 1 when S_PERR_L is asserted and bit 6 of command register
is set
24
Data Parity Error
Detected
R/WC
Reset to 0
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