參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 67/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
57
August 22, 2002 – Revision 1.02
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8150. The shift
register can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock
outputs or tied HIGH to force all secondary clock outputs HIGH. Table 11-2 shows the
format of the serial stream.
Table 11-2. GPIO Serial Data Format
Bit
[1:0]
[3:2]
[5:4]
[7:6]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Description
S_CLKOUT
Slot 0 PRSNT#[1:0] or device 0
Slot 1 PRSNT#[1:0] or device 1
Slot 2 PRSNT#[1:0] or device 2
Slot 3 PRSNT#[1:0] or device 3
Device 4
Device 5
Device 6
Device 7
Device 8
PI7C8150 S_CLKIN
Reserved
Reserved
0
1
2
3
4
5
6
7
8
9
NA
NA
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control
the S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that
indicates that a card is present in the slot and therefore the secondary clock for that slot is
not masked. If these clocks are connected to devices and not to slots, one or both of the bits
should be tied low to enable the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for
one device. These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1
disables the clock.
Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8150’s
S_CLKIN input.
If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8150’s
S_CLKIN input can be rearranged from the assignment shown here. However, it is
important that the serial data stream format match the assignment of S_CLKOUT.
The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits
are tied high to disable their respective secondary clocks because those clocks are not
connected to anything. The next bit is tied LOW because that secondary clock output is
connected to the PI7C8150 S_CLKIN input. When the secondary reset signal, S_RST_L, is
detected asserted and the primary reset signal, P_RST_L, is detected deasserted, PI7C8150
drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift register. On
the next cycle, PI7C8150 drives GPIO[2] HIGH to perform a shift operation. This shifts the
clock mask into MSK_IN; the most significant bit is shifted in first, and the least
significant bit is shifted in last.
After the shift operation is complete, PI7C8150 tri-states the GPIO signals and can deassert
S_RST_L if the secondary reset bit is clear. PI7C8150 then ignores MSK_IN. Control of
the GPIO signal now reverts to PI7C8150 GPIO control registers. The clock disable mask
can be modified subsequently through a configuration write command to the secondary
clock control register in device-specific configuration space.
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