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參數資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數： | 78/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
68
August 22, 2002 – Revision 1.02
26:25
DEVSEL_L
timing
R/O
DEVSEL# timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs on
its secondary interface
27
Signaled Target
Abort
R/WC
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary
interface are terminated with target abort
28
Received Target
Abort
R/WC
Reset to 0
Set to 1 (by a master) when transactions on its secondary interface
are terminated with Master Abort
29
Received Master
Abort
R/WC
Reset to 0
Set to 1 when S_SERR_L is asserted
30
Received System
Error
R/WC
Reset to 0
Set to 1 when address or data parity error is detected on the
secondary interface
31
Detected Parity
Error
R/WC
Reset to 0
14.1.17
MEMORY BASE REGISTER – OFFSET 20h
Bit
3:0
Function
Type
R/O
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
15:4
Memory Base
Address [15:4]
R/W
Reset to 0
14.1.18
MEMORY LIMIT REGISTER – OFFSET 20h
Bit
19:16
Function
Type
R/O
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
31:20
Memory Limit
Address [31:20]
R/W
14.1.19
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
Bit
Function
Type
Description
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