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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 65/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
55
August 22, 2002 – Revision 1.02
9
CLOCKS
This chapter provides information about the clocks.
9.1
PRIMARY CLOCK INPUTS
PI7C8150 implements a primary clock input for the PCI interface. The primary interface is
synchronized to the primary clock input, P_CLK, and the secondary interface is
synchronized to the secondary clock. The secondary clock is derived internally from the
primary clock, P_CLK. PI7C8150 operates at a maximum frequency of 66 MHz.
9.2
SECONDARY CLOCK OUTPUTS
PI7C8150 has 10 secondary clock outputs, S_CLKOUT[9:0] that can be used as clock
inputs for up to nine external secondary bus devices. The S_CLKOUT[9:0] outputs are
derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a
minimum of 0ns. This is the rule for using secondary clocks:
Each secondary clock output is limited to no more than one load.
10
GENERAL PURPOSE I/O INTERFACE
The PI7C8150 implements a 4-pin general purpose I/O interface. During normal operation,
device specific configuration registers control the GPIO interface. The GPIO interface can
be used for the following functions:
During secondary interface reset, the GPIO interface can be used to shift in a 16-bit
serial stream that serves as a secondary bus clock disable mask.
Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8150 to a
halt through hardware, permitting live insertion of option cards behind the PI7C8150.
10.1
GPIO CONTROL REGISTERS
During normal operation, the following device specific configuration registers control the
GPIO interface:
The GPIO output data register
The GPIO output enable control register
The GPIO input data register
These registers consist of five 8-bit fields:
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