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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 64/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
54
August 22, 2002 – Revision 1.02
8.2.2
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit
31=0). Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0)
clocks.
If the current master occupies the bus and other masters are waiting, the current master will
be preempted by removing its grant (GNT#) after the next master waits for the time-to-
preempt.
8.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL
ARBITER
The internal arbiter is disabled when the secondary bus central function control pin,
S_CFN_L, is tied HIGH. An external arbiter must then be used.
When S_CFN_L is tied HIGH, PI7C8150, reconfigures two pins to be external request and
grant pins. The S_GNT_L[0] pin is reconfigured to be the external request pin because it’s
an output. The S_REQ_L[0] pin is reconfigured to be the external grant pin because it’s an
input. When an external arbiter is used, PI7C8150 uses the S_GNT_L[0] pin to request the
secondary bus. When the reconfigured S_REQ_L[0] pin is asserted LOW after PI7C8150
has asserted S_GNT_L[0], PI7C8150 initiates a transaction on the secondary bus one cycle
later. If grant is asserted and PI7C8150 has not asserted the request, PI7C8150 parks AD,
CBE and PAR pins by driving them to valid logic levels.
The unused secondary bus grant outputs, S_GNT_L[8:1] are driven HIGH. The unused
secondary bus request inputs, S_REQ_L[8:1], should be pulled HIGH.
8.2.4
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value
while the bus is idle. In general, the device implementing the bus arbiter is responsible for
parking the bus or assigning another device to park the bus. A device parks the bus when
the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD
and CBE signals should be driven first, with the PAR signal driven one cycle later.
PI7C8150 parks the primary bus only when P_GNT_L is asserted, P_REQ_L is de-
asserted, and the primary PCI bus is idle. When P_GNT_L is de-asserted, PI7C8150 3-
states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C8150 is
parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C8150
can start the transaction on the next PCI clock cycle by asserting P_FRAME_L if
P_GNT_L is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the
last master that used the PCI bus. That is, PI7C8150 keeps the secondary bus grant asserted
to a particular master until a new secondary bus request comes along. After reset,
PI7C8150 parks the secondary bus at itself until transactions start occurring on the
secondary bus. Offset 48h, bit 1, can be set to 1 to park the secondary bus at PI7C8150. By
default, offset 48h, bit 1, is set to 0. If the internal arbiter is disabled, PI7C8150 parks the
secondary bus only when the reconfigured grant signal, S_REQ_L[0], is asserted and the
secondary bus is idle.
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