參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 57/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
47
August 22, 2002 – Revision 1.02
Table 7–6 shows assertion of S_PERR_L that is set under the following conditions:
PI7C8150 is either the target of a write transaction or the initiator of a read transaction
on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C8150 detects a data parity error on the secondary bus or detects P_PERR_L
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
Table 7-6. Assertion of S_PERR#
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
2
0
X
= don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Table 7–7 shows assertion of P_SERR_L. This signal is set under the following
conditions:
PI7C8150 has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
PI7C8150 did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
The SERR_L enable bit must be set in the command register.
Table 7-7. Assertion of P_SERR# for Data Parity Errors
P_SERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
1 (de-asserted)
1
1
1
1
0
2
(asserted)
0
3
1
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
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