參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 11/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
1
August 22, 2002 – Revision 1.02
1
INTRODUCTION
Product Description
The PI7C8150 is Pericom Semiconductor’s third-generation PCI-PCI Bridge.
It is designed to be fully compliant with the 32-bit, 66MHz implementation of
the
PCI Local Bus Specification, Revision 2.2.
The PI7C8150 supports only synchronous
bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the
Secondary Buses operating at either 33MHz or 66MHz. The Primary and Secondary Bus
can also operate in concurrent mode, resulting in added increase in system performance.
Concurrent bus operation off-loads and isolates unnecessary traffic from the Primary Bus,
thereby enabling a master and a target device on the Secondary PCI Bus to communicate
even while the Primary Bus is busy.
Product Features
32-bit Primary and Secondary Ports run up to 66MHz
Compliant with the
PCI Local Bus Specification, Revision 2.2
Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1
.
-
All I/O and memory commands
-
Type 1 to Type 0 configuration conversion
-
Type 1 to Type 1 configuration forwarding
-
Type 1 configuration write to special cycle conversion
Compliant with the
Advanced Configuration Power Interface (ACPI) Specification.
Compliant with the
PCI Power Management Specification, Revision 1.0.
Concurrent Primary to Secondary Bus operation and independent intra-Secondary Port
channel to reduce traffic on the Primary Port
Provides internal arbitration for one set of nine secondary bus masters
-
Programmable 2-level priority arbiter
-
Disable control for use of external arbiter
Supports posted write buffers in all directions
Two 128 byte FIFO’s for delay transactions
Two 128 byte FIFO’s for posted memory transactions
Enhanced address decoding
-
32-bit I/O address range
-
32-bit memory-mapped I/O address range
-
VGA addressing and VGA palette snooping
-
ISA-aware mode for legacy support in the first 64KB of I/O address range
Interrupt handling
-
PCI interrupts are routed through an external interrupt concentrator
Supports system transaction ordering rules
Extended commercial temperature range 0°C to 85°C
IEEE 1149.1 JTAG interface support
3.3V core; 3.3V and 5V signaling
208-pin FQFP package
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