- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367908 > PERICOMPI7C8150 (Pericom Semiconductor Corp.) 2-Port PCI-to-PCI Bridge PDF資料下載
參數(shù)資料
| 型號(hào)： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 85/106頁 |
| 文件大小： | 904K |
| 代理商： | PERICOMPI7C8150 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁當(dāng)前第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
75
August 22, 2002 – Revision 1.02
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS
REGISTER – OFFSET 58h
Bit
Function
Upstream
Memory Limit
Address
Type
Description
Defines bits [63:32] of the upstream memory limit
31:0
R/W
Reset to 0
14.1.38
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it is unable to
transfer any read data from the target after 2
attempts.
1
Posted Write
Parity Error
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it is unable to
transfer delayed write data after 2
attempts.
2
Posted Write
Non-Delivery
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
3
Target Abort
During Posted
Write
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it receives a
master abort when attempting to deliver posted write data.
4
Master Abort On
Posted Write
R/W
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls PI7C8150’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
attempts.
5
Delayed Write
Non-Delivery
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PESDXL2BT | Low capacitance double bidirectional ESD protection diodes in SOT23 |
| PESDXL2UM | LJT 23C 21#20 2#16 PIN RECP |
| PETAM1270BK300R | BRAID SLEEVING 300M |
| PETAM1270BK50C | 5V RS232 Transceiver with One Receiver Active in SHUTDOWN |
| PETAM1901BK200R | BRAID SLEEVING 300M |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PERINCSPRT5PKM | 制造商:Dialogic Corporation 功能描述:SERVICE;5PK;PERINCIDENT;HW;SUP |
| PER-M18 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Desktop Stand For ONYX-150/ 153/ 154/ 172/ 192/ 1722/ 1922/ 2122/ 2215 (VESA 100) |
| PER-M20 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Desktop Stand For ONYX-170/ 172/ 173/ 174/ 175/ 175S/175X/ 175V/ 190/ 192/ 193/ 195/ 195S/ 195X/195V/ 1722/ 1922/ 2122/ 2217/ 2219 (VESA 100/75) |
| PERMARK-FB-1/2-1.50-9 | 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-1.50-9 |
| PERMARK-FB-1/2-NO.21-9 | 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-NO.21-9 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。